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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD13280 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 features dual, 80 msps minimum sample rate channel-to-channel matching, 1% gain error 90 db channel-to-channel isolation dc-coupled signal conditioning 80 db spurious-free dynamic range selectable bipolar inputs ( 1 v and 0.5 v ranges) integral single-pole low-pass nyquist filter twos complement output format 3.3 v compatible outputs 1.85 w per channel industrial and military grade applications radar processing (optimized for i/q baseband operation) phased array receivers multichannel, multimode receivers gps antijamming receivers communications receivers dual channel, 12-bit, 80 msps a/d converter with analog input signal conditioning product description the AD13280 is a complete dual channel signal processing solution including on board amplifiers, references, adcs, and output termination components to provide optimized s ystem performance. the AD13280 has on-chip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 12-bit, 80 msps performance. the AD13280 uses innovative high- density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching, impedance control, and performance while still maintaining excellent isolation, and providing for significant board area savings. multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. the AD13280 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while still remaining general purpose. the AD13280 operates with 5.0 v for the analog signal condi- tioning with a separate 5.0 v supply for the analog-to-digital conversion, and 3.3 v digital supply for the output stage. each channel is completely independent allowing operation with independent encode and analog inputs, and maintaining mini- mal crosstalk and interference. the AD13280 is packaged in a 68-lead ceramic gull wing pack age. manufacturing is done on analog devices, inc. m il-38534 qualified manufacturers line (qml) and components are available up to class-h (?0 c to +85 c). the components are manufactured using analog devices, inc. high-speed comple- mentary bipolar process (xfcb). product highlights 1. guaranteed sample rate of 80 msps. 2. input signal conditioning included; gain and impedance match. 3. single-ended, differential, or off-module filter options. 4. fully tested/characterized full channel performance. 5. compatible with 14-bit (up to) 65 msps family. functional block diagram 100 output terminators timing 3 9 12 vref drout 12 enc enc d9a d10a d11a (msb) d0b (lsb) d1b d3b d2b d4b d5b d6b d7b d8b timing d9b 7 5 enc enc b?n d10b d11b (msb) (lsb) d0a d1a d2a d3a d4a d5a d6a d7a d8a AD13280 drouta 100 output terminators amp-in-b-2 amp-in-b-1 amp-in-a-2 amp-in-a-1 amp-out-a a?n a+in b+in amp-out-b droutb drout vref
rev. 0 C2C AD13280?pecifications (av cc = +5 v, av ee = ? v, dv cc = +3.3 v; applies to each adc with front-end amplifier unless otherwise noted.) test mil AD13280az/bz parameter temp level subgroup min typ max unit resolution 12 bits dc accuracy 1 no missing codes full iv 12 guaranteed offset error 25 c i 1 ?.2 1.0 +2.2 % fs full vi 2, 3 ?.2 1.0 +2.2 % fs offset error channel match full vi 1, 2, 3 ?.0 0.1 +1.0 % gain error 2 25 c i 1 3 ?.0 +1 % fs full vi 2, 3 ?.0 2.0 +5.0 % fs gain error channel match 25 c i 1 ?.5 0.5 +1.5 % max vi 2 ?.0 1.0 +3.0 % min vi 3 5 1.0 +5 % single-ended analog input input voltage range amp-in-x-1 full v 0.5 v amp-in-x-2 full v 1.0 v input resistance amp-in-x-1 full iv 12 99 100 101 ? amp-in-x-2 full iv 12 198 200 202 ? capacitance 25 c v 4.0 7.0 pf analog input bandwidth 3 full v 100 mhz differential analog input analog signal input range a+in to a?n and b+in to b?n 4 full v 1v input impedance 25 c v 618 ? analog input bandwidth full v 50 mhz encode input (enc, enc ) 1 differential input voltage full iv 12 0.4 v p-p differential input resistance 25 cv 10 k ? differential input capacitance 25 c v 2.5 pf switching performance maximum conversion rate 5 full vi 4, 5, 6 80 msps minimum conversion rate 5 full iv 12 20 msps aperture delay (t a )25 c v 1.5 ns aperture delay matching 25 c iv 12 250 500 ps aperture uncertainty (jitter) 25 c v 0.3 ps rms encode pulsewidth high at max conversion rate 25 c iv 12 4.75 6.25 8 ns encode pulsewidth low at max conversion rate 25 c iv 12 4.75 6.25 8 ns output delay (t od ) full v 5 ns encode, rising to data ready, rising delay full v 8.5 ns snr 1, 6 analog input @ 10 mhz 25 c i 4 67.5 70 dbfs min ii 6 64.5 dbfs max ii 5 67.5 dbfs analog input @ 21 mhz 25 c i 4 67.5 70 dbfs min ii 6 64 dbfs max ii 5 67.5 dbfs analog input @ 37 mhz 25 c i 4 63.5 65 dbfs min ii 6 61.5 dbfs max ii 5 63.5 dbfs sinad 1, 7 analog input @ 10 mhz 25 c i 4 67 69 dbfs min ii 6 63.5 dbfs max ii 5 67 dbfs analog input @ 21 mhz 25 c i 4 65 68.5 dbfs min ii 6 63 dbfs max ii 5 65 dbfs analog input @ 37 mhz 25 c i 4 54.5 59 dbfs min ii 6 53 dbfs max ii 5 54.5 dbfs
rev. 0 C3C AD13280 test mil AD13280az/bz parameter temp level subgroup min typ max unit spurious-free dynamic range 1, 8 analog input @ 10 mhz 25 c i 4 75 80 dbfs min ii 6 70 max ii 5 75 analog input @ 21 mhz 25 c i 4 68 75 dbfs min ii 6 67 max ii 5 68 analog input @ 37 mhz 25 c i 4 56 62 dbfs min ii 6 55 max ii 5 56 single-ended analog input passband ripple to 10 mhz 25 c v 0.05 db passband ripple to 25 mhz 25 c v 0.1 db differential analog input passband ripple to 10 mhz 25 c v 0.3 db passband ripple to 25 mhz 25 c v 0.82 db two-tone imd rejection 9 f in = 9.1 mhz and 10.1 mhz 25 c i 4 75 80 dbc f 1 and f 2 are ? db min ii 6 71 max ii 5 75 f in = 19.1 mhz and 20.7 mhz 25 c v 4 77 dbc f 1 and f 2 are ? db f in = 36 mhz and 37 mhz 25 c v 4 60 dbc f 1 and f 2 are ? db channel-to-channel isolation 10 25 civ 12 90 db transient response 25 cv 25 ns digital outputs 11 logic compatibility cmos dvcc = 3.3 v logic ??voltage full i 1, 2, 3 2.5 dvcc ?0.2 v logic ??voltage full i 1, 2, 3 0.2 0.5 v dvcc = 5 v logic ??voltage full v dvcc ?0.3 v logic ??voltage full v 0.35 v output coding two? complement power supply av cc supply voltage 12 full iv 4.85 5.0 5.25 v i (av cc ) current full i 1, 2, 3 310 338 ma av ee supply voltage 12 full iv ?.25 ?.0 ?.75 v i (av ee ) current full i 1, 2, 3 38 49 ma dv cc supply voltage 12 full iv 3.135 3.3 3.465 v i (dv cc ) current full i 1, 2, 3 34 46 ma i cc (total) supply current per channel full i 1, 2, 3 369 433 ma power dissipation (total) full i 1, 2, 3 3.72 4.05 w power supply rejection ratio (psrr) full v 0.01 % fsr/% v s notes 1 all ac specifications tested by driving encode and encode differentially. single-ended input: amp-in-x-1 = 1 v p-p, amp-in-x-2 = gnd. 2 gain tests are performed on amp-in-x-1 input voltage range. 3 full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is reduced by 3 db. 4 for differential input: +in = 1 v p-p and ?n = 1 v p-p (signals are 180 out of phase). for single-ended input: +in = 2 v p-p and = ?n = gnd. 5 minimum and maximum conversion rates allow for variation in encode duty cycle of 50% 5%. 6 analog input signal power at ? dbfs; signal-to-noise ratio (snr) is the ratio of signal level to total noise (first five harmo nics removed). encode = 80 msps. snr is reported in dbfs, related back to converter full scale. 7 analog input signal power at ? dbfs; signal-to-noise and distortion (sinad) is the ratio of signal level to total noise + harm onics. encode = 80 msps. sinad is reported in dbfs, related back to converter full scale. 8 analog input signal at ? dbfs; sfdr is ratio of converter full scale to worst spur. 9 both input tones at ? dbfs; two tone intermodulation distortion (imd) rejection is the ratio of either tone to the worst third order intermod product. 10 channel-to-channel isolation tested with a channel grounded and a full-scale signal applied to b channel. 11 digital output logic levels: dv cc = 3.3 v, c load = 10 pf. capacitive loads > 10 pf will degrade performance. 12 supply voltage recommended operating range. av cc may be varied from 4.85 v to 5.25 v. however, rated ac (harmonics) performance is valid only over the range av cc = 5.0 v to 5.25 v. specifications subject to change without notice.
rev. 0 AD13280 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD13280 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings electrical 1 av cc voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 7 v av ee voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ? v to 0 v dv cc voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 7 v analog input voltage . . . . . . . . . . . . . . . . . . . . . v ee to v cc analog input current . . . . . . . . . . . . . . ?0 ma to +10 ma digital input voltage (encode) . . . . . . . . . . . . . 0 to v cc encode, encode differential voltage . . . . . . . . 4 v max digital output current . . . . . . . . . . . . . . ?0 ma to +10 ma environmental 2 operating temperature (case) . . . . . . . . . ?0 c to +85 c maximum junction temperature . . . . . . . . . . . . . . . . 175 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . 300 c storage temperature range (ambient) . . ?5 c to +150 c notes 1 absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedance for ?s?package: jc 2.2 c/w; ja 24.3 c/w. test level i 100% production tested. ii 100% production tested at 25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested with temperature at 25 c: sample tested at temperature extremes. pin configuration 68-lead ceramic leaded chip carrier (es-68c) 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 961 8765 68676665646362 4321 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pin 1 identifier top view (not to scale) AD13280 agndb av ee b av cc b agndb d10a droutb agnda av ee a d0a(lsb) d1a d2a d3a d4a d5a agndb encodeb encodeb dv cc b d0b(lsb) agnda agnda amp-out-a a+in a in agnda amp-in-a-2 amp-in-a-1 agndb shield d1b d2b d3b dgnda d11b(msb) d10b d9b dgndb av cc a agndb b in b+in agndb amp-in-b-2 amp-out-b amp-in-b-1 d8b d7b d6b d5b d4b dgndb nc shield drouta d11a(msb) d8a d9a d7a d6a dgnda encodea encodea agnda agnda dv cc a nc nc nc = no connect nc ordering guide model temperature range (case) package description package option AD13280az ?5 c to +85 c 68-lead ceramic leaded chip carrier es-68c AD13280af ?5 c to +85 c 68-lead ceramic leaded chip carrier es-68c with nonconductive tie-bar 5962-0053001hxa ?0 c to +85 c 68-lead ceramic leaded chip carrier es-68c AD13280/pcb 25 c evaluation board with AD13280az
rev. 0 AD13280 C5C pin function descriptions pin no. name function 1, 35 shield internal ground shield between channels 2, 3, 9, 10, 13, 16 agnda a channel analog ground. a and b grounds should be connected as close to the device as possible. 4 a?n inverting differential input (gain = 1). 5 a+in noninverting differential input (gain = 1). 6 amp-out-a single-ended amplifier output (gain = 2). 7 amp-in-a-1 analog input for a side adc (nominally 0.5 v). 8 amp-in-a-2 analog input for a side adc (nominally 1.0 v). 11 av ee a a channel analog negative supply voltage (nominally ?.0 v or ?.2 v). 12 av cc a a channel analog positive supply voltage (nominally 5.0 v). 14 encodea complement of encode; differential input. 15 encodea encode input; conversion initiated on rising edge. 17 dv cc a a channel digital positive supply voltage (nominally 5.0 v/ 3.3 v). 18, 19, 37, 38 nc no connect. 20?5, 28?3 d0a?11a digital outputs for adc a. d0 (lsb). 26, 27 dgnda a channel digital ground. 34 drouta data ready a output. 36 droutb data ready b output. 39?2, 45?2 d0b?11b digital outputs for adc b. d0 (lsb). 43, 44 dgndb b channel digital ground. 53 dv cc b b channel digital positive supply voltage (nominally 5.0 v/ 3.3 v). 54, 57, 60, 61, 67, 68 agndb b channel analog ground. a and b grounds should be connected as close to the device as possible. 55 encodeb encode input; conversion initiated on rising edge. 56 encodeb complement of encode; differential input. 58 av cc b b channel analog positive supply voltage (nominally 5.0 v). 59 av ee b b channel analog negative supply voltage (nominally ?.0 v or ?.2 v). 62 amp-in-b-2 analog input for b side adc (nominally 1.0 v). 63 amp-in-b-1 analog input for b side adc (nominally 0.5 v). 64 amp-out-b single-ended amplifier output (gain = 2). 65 b+in noninverting differential input (gain = 1). 66 b?n inverting differential input (gain = 1).
rev. 0 AD13280 C6C frequency mhz 130 0 encode = 80msps a in = 5mhz ( 1dbfs) snr = 69.4dbfs sfdr = 81.9dbc 5101520 2530 120 110 100 90 80 70 60 50 40 30 20 10 0 2 35 40 6 3 4 5 db tpc 1. single tone @ 5 mhz frequency mhz 130 0 encode = 80msps a in = 18mhz ( 1dbfs) snr = 69.79dbfs sfdr = 76.81dbc 5101520 2530 120 110 100 90 80 70 60 50 40 30 20 10 0 35 40 db tpc 2. single tone @ 18 mhz frequency mhz 130 0 5101520 2530 120 110 100 90 80 70 60 50 40 30 20 10 0 35 40 encode = 80msps a in = 9mhz and 10mhz ( 7dbfs) sfdr = 82.77dbc db tpc 3. two tone @ 9 mhz/10 mhz encode = 80msps a in = 10mhz ( 1dbfs) snr = 69.19dbfs sfdr = 79.55dbc frequency mhz 130 0 5101520 2530 120 110 100 90 80 70 60 50 40 30 20 10 0 2 35 40 6 3 4 5 db tpc 4. single tone @ 10 mhz encode = 80msps a in = 37mhz ( 1dbfs) snr = 68.38dbfs sfdr = 57.81dbc frequency mhz 130 0 5101520 2530 120 110 100 90 80 70 60 50 40 30 20 10 0 2 35 40 6 3 4 5 db tpc 5. single tone @ 37 mhz encode = 80msps a in = 19mhz and 20mhz ( 7dbfs) sfdr = 74.41dbc frequency mhz 130 0 5101520 2530 120 110 100 90 80 70 60 50 40 30 20 10 0 35 40 db tpc 6. two tone @ 19 mhz/20 mhz typical performance characteristics
rev. 0 AD13280 C7C 1.0 0 512 encode = 80msps dnl max = 0.688 codes dnl min = 0.385 codes 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 1024 1536 2048 2560 3072 3584 4096 lsb tpc 7. differential nonlinearity frequency mhz 1.0 3.5 dbfs 10 9 8 7 6 5 4 3 2 1 0 6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0 encode = 80msps roll-off = 0.0459db tpc 8. passband ripple to 25 mhz 3 encode = 80msps inl max = 0.562 codes inl min = 0.703 codes 2 0 2 3 1 1 0 512 1024 1536 2048 2560 3072 3584 4096 lsb ()*1
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rev. 0 AD13280 C8C definition of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between a differential crossing of encode and encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capaci- tance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code from an ideal 1 lsb step. encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the encode pulse should be left in logic ??state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. at a given clock rate, these specs define an acceptable encode duty cycle. harmonic distortion the ratio of the rms signal amplitude to the rms value of the worst harmonic component. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a ?est straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of encode and encode command and the time when all output data bits are within valid logic levels. overvoltage recovery time the amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. may be reported in db (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. may be rep orted in db (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). spurious-free dynamic range the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. transient response the time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the ana- log input. two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. t a a in enc, enc d[11:0] dry n n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4 n 3n 2n 1n t encl t ench t enc t e_dr t od figure 1. timing diagram
rev. 0 AD13280 C9C amp-in-x-1 100 100 to ad8037 amp-in-x-2 figure 2. single-ended input stage loads loads encode 10k 10k encode av cc av cc 10k 10k av cc av cc figure 3. encode inputs current mirror current mirror dr out dv cc v ref dv cc figure 4. digital output stage current mirror current mirror d0 d11 100 dv cc v ref dv cc figure 5. digital output stage theory of operation the AD13280 is a high-dynamic range 12-bit, 80 mhz pipeline delay (three pipelines) analog-to-digital converter. the custom analog input section provides input ranges of 1 v and 2 v p-p and input impedance configurations of 50 ? , 100 ? , and 200 ? . the AD13280 employs four monolithic adi components per channel (ad8037, ad8138, ad8031, and a custom adc ic), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 12-bit analog-to-digital converter. in the single-ended input configuration the input signal is passed through a precision laser trimmed resistor divider allowing the user to externally select operation with a full-scale signal of 0.5 v, or 1.0 v by choosing the proper input terminal for the application. the result of the resistor divider is to apply a full- scale input approximately 0.4 v to the noninverting input of the internal ad8037 amplifier. the AD13280 analog input includes an ad8037 amplifier f eatur- ing an innovative architecture that maximizes the dynamic range capability on the amplifiers?inputs and outputs. the ad8037 amplifier provides a high input impedance and gain for driving the ad8138 in a single-ended to differential amplifier configura- tion. the ad8138 has a ? db bandwidth at 300 mhz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. the ad8138 differential outputs help balance the differential inputs to the custom adc maximizing the performance of the device. the ad8031 provides the buffer for the internal reference analog- to-digital converter. the internal reference voltage of the custom adc is designed to track the offsets and drifts and is used to ensure matching over an extended temperature range of operation. the reference voltage is connected to the output common-mode input on the ad8138. this reference voltage sets the output common mode on the ad8138 at 2.4 v, which is the midsupply level for the adc. the custom adc has complementary analog input pins, ain and ain. each analog input is centered at 2.4 v and should swing 0.55 v around this reference. since ain and ain are 180 degrees out of phase, the differential analog input signal is 2.2 v peak-to-peak. both analog inputs are buffered prior to the first track-and-hold. the custom adc digital outputs drive 100 ? series resistors (fig- ure 5). the result is a 12-bit parallel digital cmos-compatible word, coded as two? complement. using the single-ended input the AD13280 has been designed with the user? ease of opera- tion in mind. multiple input configurations have been included on-board to allow the user a choice of input signal levels and input impedance. the standard inputs are 0.5 v and 1.0 v. the user can select the input impedance of the AD13280 on any input by using the other inputs as alternate locations for the gnd. the following chart summarizes the impedance options available at each input location. amp-in-x-1 = 100 ? when amp-in-x-2 is open. amp-in-x-1 = 50 ? when amp-in-x-2 is shorted to gnd. amp-in-x-2 = 200 ? when amp-in-x-1 is open. each channel has two analog inputs amp-in-a-1 and amp- in-a-2 or amp-in-b-1 and amp-in-b-2. use amp-in-a-1
rev. 0 AD13280 C10C or amp-in-b-1 when an input of 0.5 v full scale is desired. use amp-in-a-2 or amp-in-b-2 when 1 v full scale is desired. each channel has an amp-out which must be tied to either a noninverting or inverting input of a differential amplifier with the remaining input grounded. for example, side a, amp-out-a (pin 6) must be tied to a+in (pin 5) with a?n (pin 5) tied to ground for noninverting operation or amp-out-a (pin 6) tied to a?n (pin 4) with a+in (pin 5) tied to ground for inverting operation. using the differential input each channel of the AD13280 was designed with two optional differential inputs, a+in, a?n and b+in, b?n. the inputs provide system designers with the ability to bypass the ad8037 amplifier and drive the ad8138 directly. the ad8138 differen- tial adc driver can be deployed in either a single-ended or differential input configuration. the differential analog inputs have a nominal input impedance of 620 ? and nominal full- scale input range of 1.2 v p-p. the ad8138 amplifier drives a differential filter and the custom analog-to-digital converter. the differential input configuration provides the lowest even-order harmonics and signal-to-noise (snr) performance improvement of up to 3 db (snr = 73 dbfs). exceptional care was taken in the layout of the differential input signal paths. the differential input transmission line characteristics are matched and balanced. equal attention to system level signal paths must be provided in order to realize significant performance improvements. applying the AD13280 encoding the AD13280 the AD13280 encode signal must be a high quality, extremely low phase noise source, to prevent degradation of performance. maintaining 12-bit accuracy at 80 msps places a premium on encode clock phase noise. snr performance can easily degrade 3 db to 4 db with 37 mhz input signals when using a high-jitter clock source. see analog devices?application note an-501, ?perture uncertainty and adc system performance?for complete details. for optimum performance, the AD13280 must be clocked differentially. the encode signal is usually ac-coupled into the encode and encode pins via a transformer or capacitors. these pins are biased internally and require no addi- tional bias. shown below is one preferred method for clocking the AD13280. the clock source (low jitter) is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the AD13280 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD13280, and limits the noise presented to the encode inputs. a crystal clock oscillator can also be used to drive the rf transformer if an appropriate limited resistor (typically 100 ? ) is placed in the series with the primary. t1-4t 100 0.1 f encode encode AD13280 hsms2812 diodes clock source figure 6. crystal clock oscillatordifferential encode if a low jitter ecl/pecl clock is available, another option is to ac-couple a differential ecl/pecl signal to the encode input pins as shown below. a device that offers excellent jitter perfor- mance is the mc100lvel16 (or same family) from motorola. encode encode AD13280 0.1 f ecl/ pecl vt vt 0.1 f figure 7. differential ecl for encode jitter consideration the signal-to-noise ratio (snr) for any adc can be predicted. when normalized to adc codes, equation 1 accurately predicts the snr based on three terms. these are jitter, average dnl error, and thermal noise. each of these terms contributes to the noise within the converter. snr f t v n analog rms noise rms n = + () ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? log ( ) / 20 1 2 2 2 2 2 12 j (1) f analog = analog input frequency t j rms = rms jitter of the encode (rms sum of encode source and internal encode circuitry) = average dnl of the adc (typically 0.50 lsb) n = number of bits in the adc v noise rms = v rms noise referred to the analog input of the adc (typically 5 lsb) for a 12-bit analog-to-digital converter like the AD13280, aper- ture jitter can greatly affect the snr performance as the analog frequency is increased. the chart below shows a family of curves that demonstrates the expected snr performance of the AD13280 as jitter increases. the chart is derived from the above equation. for a complete discussion of aperture jitter, please consult ana- log devices application note an-501, aperture uncertainty and adc system performance. clock jitter ps 0.0 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 snr dbfs 60 a in = 5mhz a in = 10mhz a in = 20mhz a in = 37mhz 61 62 63 64 65 66 67 68 69 70 71 59 58 3.8 4.0 figure 8. snr vs. jitter
rev. 0 AD13280 C11C power supplies care should be taken when selecting a power source. linear sup- plies are strongly recommended. switching supplies tend to have radiated components that may be received by the AD13280. each of the power supply pins should be decoupled as closely as possible to the package, using 0.1 f chip capacitors. the AD13280 has separate digital and analog power supply pins. the analog supplies are denoted av cc and the digital supply pins are denoted dv cc . av cc and dv cc should be separate power supplies because the fast digital output swings can couple switching current back into the analog supplies. note that av cc must be held within 5% of 5 v. the AD13280 is specified for dv cc = 3.3 v as this is a common supply for digital asics. output loading care must be taken when designing the data receivers for the AD13280. the digital outputs drive an internal series resistor (e.g., 100 ? ) followed by a gate like 75lcx574. to minimize capacitive loading, there should be only one gate on each output pin. an example of this is shown in the evaluation board sche- matic shown in figure 9. the digital outputs of the AD13280 have a constant output slew rate of 1 v/ns. a typical cmos gate combined with a pcb trace will have a load of approxi- mately 10 pf. therefore, as each bit switches, 10 ma (10 pf 1 v 1 ns ) of dynamic current per bit will flow in or out of the device. a full-scale transition can cause up to 120 ma (12 bits 10 ma/bit) of transient current through the output stages. these switching currents are confined between ground and the dv cc pin. standard ttl gates should be avoided since they can app reciably add to the dynamic switching currents of the AD13280. it should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. digital output timing is guaranteed with 10 pf loads. layout information the schematic of the evaluation board (figure 10) represents a typical implementation of the AD13280. the pinout of the AD13280 is very straightforward and facilitates ease of use and the implementation of high-frequency/high-resolution design practices. it is recommended that high-quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. all capacitors can be standard high-quality ceramic chip capacitors. care should be taken when placing the digital output runs. because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. internal circuitry buffers the outputs of the adc through a resistor network to eliminate the need to externally isolate the device from the receiving gate. evaluation board the AD13280 evaluation board (figure 9) is designed to provide optimal performance for evaluation of the AD13280 analog-to-digital converter. the board encompasses everything needed to ensure the highest level of performance for evaluating the AD13280. the board requires an analog input signal, encode clock, and power supply inputs. the clock is buffered on-board to provide clocks for the latches. the digital outputs and out clocks are available at the standard 40-pin connectors j1 and j2. power to the analog supply pins is connected via banana jacks. the analog supply powers the associated components and the analog section of the AD13280. the digital outputs of the AD13280 are powered via banana jacks with 3.3 v. contact the factory if additional layout or applications assistance is required. figure 9. evaluation board mechanical layout
rev. 0 AD13280 C12C bill of materials list for evaluation board qty. component name ref/des value description manufacturing part no. 2 74lcx16373mtd u7, u8 latch 74lcx16373mtd (fairchild) 1 AD13280az u1 AD13280 AD13280az 2 adp3330 u5, u6 regulator adp3330art-3.3rl7 10 bjack bj1 bj10 banana jacks 108-0740-001 (johnson components) 2 bres0805 r41, r53 25 ? 0805 sm resistor erj-6geyj 240v 4 bres0805 r38, r39, r55, r56 33 k ? 0805 sm resistor erj-6geyj 333v 28 cap2 c1, c2, c5 c10, 0.1 f 0805 sm capacitor grm 40x7r104k025bl c12, c16 c18, c20 c26, c28, c30 c38 2 cap2 c13, c27 0.47 f 0805 sm capacitor vj1206u474mfxmb 2 h40dm j1, j2 2 20 40 pin male connector tsw-120-08-g-d 6 ind2 l1 l6 47 ? sm inductor 2743019447 4 mc10el16 u2, u4, u9, u11 clock drivers mc1016ep16d 2 mc100elt23 u4, u10 ecl/ttl clock drivers sy100elt23l 8 polcap2 c3, c4, c11, c14, 10 f tantalum polar caps t491c106m016a57280 c15, c19, c29, c30 4 res2 r47 r50 0 ? 0805 sm resistor erj-6gey or 00v 6 res2 r1, r2, r5, r7, r8, r54 50 ? 0805 sm resistor erj-6geyj 510v 36 res2 r3, r4, r6, r9, r12 r15, 100 ? 0805 sm resistor erj-6geyj 101v r19 r28, r31 r36, r37, r42, r43, r44 r46 r51, r52 12 sma j3 j14 sma connectors 142-0701-201 4 standoff standoff 313- 2477-016 (johnson components) 4 screws screws (standoff) mpms 004 0005 ph (building fasteners) 1 pcb AD13280 eval board (rev. b) gs03361
rev. 0 AD13280 C13C agnda 10 agnda 11 12 5vaa 13 +5vaa 14 d0a(lsb) 15 d1a 16 d2a 17 d3a 18 d4a 19 d5a 20 21 22 23 24 25 dgnda 26 agndb 60 59 58 agndb 57 56 55 54 53 encbb 52 encb 51 +3.3vdb 50 d11b(msb) 49 d7b 48 d6b 47 d5b 46 d4b 45 dgndb 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 agnda amp in a 2 a+in a in agnda shield agndb agndb d10a d11a(msba) shield drbout nc nc d1b d2b d3b dgndb u1 AD13280 d1a d2a d3a d4a d5a d0a dgnda agnda agnda encab nc nc enca agnda +3vda nc0a nc1a agnda enca encab 5vaa c9 0.1 f c10 0.1 f c36 0.1 f out 3.3vda c34 0.1 f +5vaa agnda agnda c35 0.1 f agnda amp in a 1 amp out a agnda agndb b in b+in amp out b amp in b 1 amp in b 2 5.2vab +5vab dgnda agndb d8b d9b d10b d0b(lsbb) draout d9a d8a d7a d6a dgnda d10a d11a drbout nc0b nc1b d1b d2b d3b dgndb d0b draout d9a d8a d7a d6a dgnda e56 e55 lidb e65 e48 e40 dgnda dgndb e69 e70 e49 agnda e51 e50 e72 e74 e77 e75 e73 e71 j4 sma agnda j3 sma e76 e78 e83 e81 e79 agnda j9 sma agnda j13 sma agnda e68 e66 agndb e54 e53 j7 sma agndb e86 e85 e52 agndb agndb j14 sma agndb j8 sma agndb j6 sma dgndb 5vab c33 0.1 f c18 0.1 f c37 0.1 f out 3.3vdb c17 0.1 f +5vab agndb agndb c38 0.1 f agndb agndb encbb encb d11b d7b d6b d5b d4b dgndb agndb d8b d9b d10b e67 lida e80 e82 e84 nc = no connect l1 c29 10 f +3vda u7 c62 0.1 f 47 20% @100mhz dgnda dut 3.3vda bj10 1 l2 c30 10 f +3vdb u8 c16 0.1 f 47 20% @100mhz dgndb dut 3.3vdb bj9 1 l3 c3 10 f +3vaa u1 c20 0.1 f 47 20% @100mhz agnda +5vaa bj6 1 agnda l4 c4 10 f +5vab u1 c21 0.1 f 47 20%@100mhz agndb +5vab bj5 1 agndb l5 c11 10 f 5vaa u1 c32 0.1 f 47 20%@100mhz agnda 5vaa bj2 1 agnda l6 c19 10 f 5vab u1 c31 0.1 f 47 20%@100mhz agndb 5vab bj1 1 agndb figure 10a. evaluation board
rev. 0 AD13280 C14C msb b11b b10b b9b b8b b7b b6b f1b dgndb f2b lsb b0b b1b b2b b3b dgndb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 b5b b4b c14 10 f buflatb r2 50 e64 e63 e62 draout 3.3vdb dgndb j2 h40dn f3b f0b u7 29 30 31 32 33 34 35 36 37 38 39 40 43 44 45 46 47 48 41 42 r11, dni 25 26 27 28 113 112 vcc 111 110 gnd 19 18 17 16 gnd 15 13 12 gnd 11 10 14 vcc le2 115 114 gnd o13 o12 vcc o11 o10 gnd o9 o8 o7 o6 gnd o5 o3 o2 gnd o1 o0 o4 vcc oe2 o15 o14 gnd 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 24 23 22 21 dut 3.3vdb dgndb dgndb dgndb dut 3.3vdb dgndb dgndb r10, dni r30, dni r29, dni r28, 100 r27, 100 r26, 100 r12, 100 r9, 100 r35, 100 r34, 100 r33, 100 r32, 100 r31, 100 r25, 100 le1 oe1 dut 3.3vdb dgndb dgndb dgndb dut 3.3vdb dgndb r49 0 r50 0 dgndb r8 50 latchb e57 nc0b nc1b lsb d0b d1b d2b d3b d4b d5b d6b d7b d8b d9b d10b msb d11b f0b f1b f2b f3b b0b (lsb) b1b b2b b3b b4b b5b b6b b7b b8b b9b b10b b11b (msb) dgndb 74lcx16374 r36, 100 msb b11a b10a b9a b8a b7a b6a f1a dgnda f2a lsb b0a b1a b2a b3a dgnda 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 b5a b4a c15 10 f buflata r5 50 e61 e60 e59 draout 3.3vda dgnda h40dm j1 f3a f0a u8 29 30 31 32 33 34 35 36 37 38 39 40 43 44 45 46 47 48 41 42 r18, dni 25 26 27 28 113 112 vcc 111 110 gnd 19 18 17 16 gnd 15 13 12 gnd 11 10 14 vcc le2 115 114 gnd o13 o12 vcc o11 o10 gnd o9 o8 o7 o6 gnd o5 o3 o2 gnd o1 o0 o4 vcc oe2 o15 o14 gnd 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 24 23 22 21 dut 3.3vda dgnda dgnda dgnda dut 3.3vda dgnda dgnda r17, dni r40, dni r44, dni r45, 100 r46, 100 r15, 100 r14, 100 r13, 100 r24, 100 r23, 100 r22, 100 r21, 100 r20, 100 r19, 100 r15, 100 le1 oe1 dut 3.3vda dgnda dgnda dgnda dut 3.3vda dgnda r47 0 r48 0 dgnda r7 50 latcha e58 nc0a nc1a lsb d0a d1a d2a d3a d4a d5a d6a d7a d8a d9a d10a msb d11a f0a f1a f2a f3a b0a (lsb) b1a b2a b3a b4a b5a b6a b7a b8a b9a b10a b11a (msb) dgnda 74lcx16374 figure 10b. evaluation board
rev. 0 AD13280 C15C nc = no connect vcc q vee nc d vbb u2 mc10el16 agnda 1 2 3 4 8 7 6 5 out nr in sd u5 3 5 1 err gnd 4 adp3330 5 agnda db qb c13 0.47 f +3.3va c7 0.1 f c8 0.1 f encab enca agnda r43 100 agnda r56 33k nc = no connect vcc q vee nc d vbb u3 mc10el16 1 2 3 4 8 7 6 5 db qb nc = no connect vcc q0 vee nc d vbb u4 mc100ept23 1 2 3 4 8 7 6 5 db q1 +3.3vda c6 0.47 f r55 33k dgnda c2 0.1 f r41 25 j12 sma j5 encode sma r1 50 c1 0.1 f agnda agnda agnda dgnda dgnda agnda r3 100 r4 100 dgnda dgnd c5 0.47 f +3.3vda latcha buflata e23 e19 +5vaa r42 100 2 e17 e27 e25 e21 e32 e44 e42 e10 e33 e6 e18 e28 e26 e20 e31 e43 e41 e9 e34 e5 dgnda agnda e38 e29 e1 e36 e14 e37 e30 e2 e35 e13 dgndb agndb so1 so2 so4 so5 so6 e45 e3 e46 e4 so3 e15 e7 e16 e12 dgnda dgndb e11 e39 e8 e47 dgnda dgndb agndb 1 bj3 agnda 1 bj4 dgndb 1 bj7 dgndb dgnda 1 bj8 dgnda nc = no connect vcc q vee nc d vbb u11 mc10el16 agndb 1 2 3 4 8 7 6 5 out nr in sd u6 3 5 1 err gnd 4 adp3330 5 agndb db qb c27 0.47 f +3.3vb c24 0.1 f c28 0.1 f encbb encb agndb r52 100 agnda r38 33k nc = no connect vcc q vee nc d vbb u9 mc10el16 1 2 3 4 8 7 6 5 db qb nc = no connect vcc q0 vee nc d vbb u10 mc100ept23 1 2 3 4 8 7 6 5 db q1 +3.3vdb c25 0.47 f r39 33k dgndb c23 0.1 f r53 25 j11 sma j10 encode sma r54 50 c22 0.1 f agndb agndb agndb dgndb dgndb dgndb r37 100 dgndb dgndb c26 0.1 f +3.3vda latchb buflatb e24 e22 +5vab r51 100 2 r6 100 figure 10c. evaluation board
rev. 0 AD13280 C16C figure 11a. top silk figure 11b. top layer
rev. 0 AD13280 C17C figure 11c. gnd1 figure 11d. gnd2
rev. 0 AD13280 C18C figure 11e. bottom silk figure 11f. bottom layer
rev. 0 AD13280 C19C outline dimensions dimensions shown in inches and (mm). 68-lead ceramic leaded chip carrier (es-68c) 1.190 (30.23) 1.180 (29.97) sq 1.170 (29.72) pin 1 10 26 9 61 60 43 27 44 top view (pins down) 0.800 (20.32) bsc 0.960 (24.38) 0.950 (24.13) sq 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.175 (4.45) max 0.235 (5.97) max detail a 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) 1.070 (27.18) min
rev. 0 C20C c02386C2.5C4/01(0) printed in u.s.a. AD13280 outline dimensions dimensions shown in inches and (mm). 68-lead ceramic leaded chip carrier with non-conductive tie-bar (es-68c) detail a 0.010 (0.254) 30 0.050 (1.27) 0.020 (0.508) 0.175 (4.45) max 0.235 (5.97) max detail a 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) pin 1 top view (pins down) 0.800 (20.32) bsc 0.960 (24.38) 0.950 (24.13) sq 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.040 (1.02) 45 0.015 (0.3) 45 3 pls 0.040 (1.02) r typ 0.350 (8.89) typ 2.000 (8.89) typ

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